The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use either a combination of logic gates or a look-up table to perform a logic operation. Programmable devices also include a number of functional cells having specialized devices adapted to a specific operations, including memory cells adapted to store information, multiply and accumulate (MAC) cells adapted to perform arithmetic operations, and communication cells adapted to communicate with external devices.
The logic cells and functional cells are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional cells. By configuring the combination of logic cells, functional cells, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function. The configuration of the logic cells, functional cells, and the switching cells, referred to as the device configuration, is stored in a configuration memory included in the programmable device. The device configuration can be loaded from an external device, such as an external non-volatile memory device or a testing device, into the configuration memory of the programmable device, thereby configuring the programmable device to perform the desired function.
The memory cells of a programmable device can be implemented as a multiple port random-access memory (RAM) device. A multiple port RAM device allows several memory read or write operations to occur simultaneously. For example, a dual-port RAM device allows for two simultaneous memory operations. Similarly, a four-port RAM device allows for four simultaneous memory operations. Typically, each port of a multiple port memory cell will have its own data and address lines.
To allow for greater flexibility in utilizing memory cells, a multiple-port memory cell can be partitioned by a device configuration into several single port memory devices. For example, a dual-port memory cell can be partitioned into two single-port memory devices. In general, an M-port memory cell can be partitioned into as many as M single port memory devices. Partitioning a memory cell allows for a greater variety of data to be stored in a memory cell without requiring complicated memory management schemes.
When a memory cells in partitioned in several single port memories, care must be taken so that data intended for one partition is not inadvertently stored in a portion of the memory cell assigned to another partition. This problem, referred to as cross-addressing, can be prevented by aligning memory partitions along memory address boundaries and assigning fixed values to some of the address lines of each port. By fixing the values of some its address lines, a port cannot access the portion of a memory cell outside of its assigned partition. The fixed values assigned to address lines of each port of a memory cell are typically set by the configuration data of the programmable device, and must remain at their assigned values during the programmable device's reset and clear operations, as well as during the programmable device's normal operation.
A prior implementation for partitioning a multiple port memory cell into one or more single port memory partitions uses the programmable device's logic cells to drive the desired fixed values onto the address lines of each memory port of the memory cell. This implementation typically requires a separate logic cell for each address line to be fixed. Additionally, each logic cell used for memory partitioning must be connected with the appropriate address line via the configurable switching circuit. As a programmable device has only a limited number of logic cells available and the configurable switching circuit has a limited capacity to route connections within the programmable device, the use of logic cells to partition memory cells wastes precious programmable device resources.
It is therefore desirable to enable a programmable device to divide multiple port memory cells into one or more single port memory partitions without consuming expensive programmable device resources and while preventing cross addressing problems. It is further desirable that the memory partitioning specified by a device configuration remains in effect during all modes of operation of the programmable device, including reset and clear operation. It is additionally desirable for more complicated memory addressing functions, such as address bit inversions, to be enabled without requiring expensive programmable device resources.